EVENT HANDLER Work Sheets I HARDWARE a) Front -- front b) Back Panel -- auxbp c) Busy -- busy d) FIFO -- FIFO e) Downloading -- load II Assembler Firmware a) Reg -- reg b) bit -- bit c) op-codes -- opco d) interrupt -- inter III Assembler a) higher level -- assem b) example -- examp IV Usage a) use -- use V Other Mods a) Event Handler Fixing -- fix b) hardware modifications -- mods Page 2 EVENT HANDLER FRONT PANEL o-----------------------o | EVENT | | HANDLER | | | | o | | ON | |RESET LOCK | | {} {} | | | | o------ | --INPUTS-- | | REQ | | (1) (2) | ( ) | / | | | 1-6 (TTL)--> | (3) (4) | -AUX- | AUXILIARY \ | | IN | CRATE | (5) (6) | ( ) | CONTROLLER | | Grant | 7-8 [NIM]--> | [7] [8] | ( ) | | | OUT | | | | | o busy | o 1 | | o stop | o 2 | LED's | o wait | | Status Indicators | o naf | o naf | | o out | o n | | o no-Q | o no-Q| | o------ | | EVENT | | ( ) [ ] | | | | ( ) [ ] o---o | |INT HOLD | | | | | | | | | | | --OUTPUTS-- | ( ) | F | | | BUSY | | | | [ ] [ ] | I | | | | | | 1,2,3 50 ohm | (1) (2) | F | | | | | | 4,5,6 TTL | (3) (4) | O | | | | | | | (5) (6) | | | | | | | 7,8 NIM | [7] [8] o---o | | | | | | | | O | o-----------------------o ^ | Active Slot Page 3 EVENT HANDLER FRONT PANEL All of the input jacks on the front panel of the Event Handler accept LEMO connectors, but there is a mix of NIM-slow and NIM-fast signal types used. INPUT OUTPUT *** TTL *** -------------- -------------- NIM-slow on (TRUE) > 2.0V > 2.0V (50 ohm) or TTL off (FALSE) < 0.8V < 0.4V INPUT OUTPUT *** NIM *** -------------- -------------- on (TRUE) <-0.3V (50 ohm) -16 ma NIM-fast -0.7V (50 ohm) off (FALSE) > -0.2V (50 ohm) 0 ma For convenience, I will refer to NIM-fast signals simply as NIM and refer to TTL/NIM-slow signals as TTL. Note that even though NIM-fast signals are accepted, they should be no shorter than about 50 ns. The Event Handler is a TTL device, and it may not see a 10 ns signal. NOTE All NIM-fast inputs or outputs are marked with a dark half circle around the jack. Inputs 1 to 6 are TTL -- they are not terminated, and if left free will float TRUE. They present less than an LS-TTL load, so you may connect fairly weak drive capability devices to them. Low power TTL devices should work. If you are using old style NIM-slow gates, you may find that you need to terminate the signals in 100 or 50 ohms to obtain a valid off. INT and EVENT (TTL) are TTL, but they have internal 100 ohm terminators. Both of these signals go to front-edge triggered devices, so the duration of the signal does not matter. A very long interrupt generates one interrupt. Inputs 7 to 8, HOLD, and EVENT (NIM) are NIM-fast inputs, and all are terminated internally in 50 ohm. EVENT is front-edge triggered, but HOLD and inputs 7,8 are levels. NOTE: Inputs 1 to 8 do not latch. You must hold them on/off until they are sampled in software. On the other hand, should you switch an input just at the moment it is being sampled, it will not adversely affect the Event Handler -- you will simply have an unpredictable outcome on the sample. EVENT and INT do latch so only the front edge is important. Page 4 GRANT IN is a TTL input with a 2000 ohm pull-up. It has been "deglitched" so that noise on the request (REQ) line will not trigger it. GRANT IN goes to a front-edge triggered circuit and is compatible with either the REQ or GRANT OUT outputs. Outputs 1 to 6, REQ, GRANT OUT, and BUSY (TTL) are TTL signals. Outputs 4 to 6 and GRANT OUT are standard TTL drives. Outputs 1 to 3 and BUSY are 50 ohm drive TTL circuits. REQ is an open-collector driven bus with at least a 2000 ohm pull-up. Outputs 7 to 8 and two BUSY (NIM) outputs are NIM-fast outputs -- they are current sources which sink 16 ma. They will drive a 50 ohm terminated line to at least -0.7V. FIFO is a standard ribbon header with pin 1 in the upper left hand corner. All signals are standard TTL. RESET -- the RESET button will cause an internal "Z", equivalent to the reset-on-power-up from the crate. This will reset all outputs and clear any Master Latches set in either AUX. (Ocassionally when one is working with two AUXs, the Event Handler will be turned on in both AUXs. If so, you must turn it off in both AUXs to turn the Event Handler off, or you may push the RESET button.) When a crate is powered up, the AUX in that crate should clear the Event Handler, wherever it is. LOCK -- the lock switch allows one to turn the Event Handler on manually or to prevent it from being turned off. This is a feature which could have importance if one were sharing a crate with someone else. Remember that you can't download the Event Handler while it is locked. REQ/GRANT -- the Event Handler requires the implementation of the REQ/GRANT logic even when it is being used with a L2 serial crate controller which does not recognize this protocol. Consequently, there MUST be a GRANT IN signal. When using an L2-CC, simply cable REQ to GRANT IN. Page 5 LED Indicators ON -- this indicator is on when the Event Handler is enabled, either through software or by the LOCK switch. BUSY -- this indicator is active whenever the Event Handler BUSY condition is satisfied. See the section on BUSY. BUSY is also present when the Event Handler is disabled. STOP -- this LED signals that the HALT condition has been set in the RIFO by the host computer (power-on will also set it). You may check it by pushing the RESET button. WAIT -- this is a dynamic indicator which should tell you a lot about the host computer. It indicates the 3/4 full condition in the FIFO. When you see this indicator, the host computer is contributing to the deadtime. A good system with a "fast" host will leave this LED dark. The LED is active also whenever the host has set the PAUSE condition in the FIFO (also set on power up). NAF -- there is a NAF LED for the Event Handler and one for each AUX. The NAF indicator for the Event Handler is on only during a NAF operation (to either AUX) and this less than 2 micro-sec lighting of the LED is normally not visible, even during continuous generation of NAF operations. The indicator for each AUX is stretched to about a millisecond, so that modest NAF activity should be visible in this indicator. If for some reason a NAF operation hangs up (you have forgotten to provide a GRANT IN signal), the LED in the Event Handler will stay on and those in the AUXs will be dark. So, if you see the Event Handler NAF indicator definitely on, something is strange. OUT -- this indicator is on only while an OUT operation is active. This time is normally only 400 ns per transfer, so you should never see this light. If you do, it is an indication that the FIFO has gone full, and you are hung up waiting for the FIFO to allow more transfers. See the sections on the FIFO and BUSY to avoid this condition. NO-Q -- this is the indication that a NAF operation has not received a "Q" response from the CAMAC module being accessed. It probably is a good idea to track this down and find out why the module is being hinky. Unfortunately, there are some modules which do not supply Q even though a quite reasonable transaction has been initiated with it. For instance, some LeCroy ADC modules will withhold Q when they feel that the channel you are reading is not valid; perhaps the signal was below threshold. Read their manuals to figure out what is up. The NO-Q LED for the Event Handler indicates the condition of NO-Q for whichever AUX it is currently attached to. This can be misleading, so look to the NO-Q LED in the individual AUXs to verify that you have a problem. N -- this is an indicator of CAMAC dataway I/O with the Event Handler when it is being accessed as a memory module. This LED should light whenever you are downloading or verifying the memory of the Event Handler. It cannot come on when the Event Handler is enabled. Page 6 EVENT HANDLER AUXILIARY CONTROLLER Back Panel Connector The diagram below is a pin schematic of the DB-25P connector on the back of the Auxiliary section of the Event Handler. The '*' after each of the labels indicates that the associated signal is low-true. In most applications the signals are held high by the crate controller, and the Event Handler uses tri-state gates to drive the lines. An 'O' by the pin indicates that the Event Handler will drive that particular line; an 'I' indicates that the crate controller will drive the line while the Event Handler will sense the line. RI* and REQ* are driven by the requesting controller but are sensed by all the controllers. Back Panel Connector Schematic 13 : : 25 12 : : 24 11 : : 23 10 : : 22 9 : : 21 8 : O 20 RI* 7 : O 19 REQ* 6 : : 18 5 : I 17 ACL* 4 : O 16 N16* N8* 3 O O 15 N4* N2* 2 O O 14 N1* GND 1 O N1*, N2*, N4*, N8*, AND N16* refer to the 5 bits for the N-line select. ACL* is the auxiliary crate lockout signal and is generated by an L2 serial crate controller to lockout any auxiliary controllers during a serial highway I/O transaction. REQ* is the request line used for the Request/Grant protocol; RI* is the request inhibit line. For controllers which honor the R/G protocol (the A2 controller and several special controllers), the Event Handler can be cabled via the front panel to have the highest priority for the CAMAC dataway or to have a lower priority. For it to have the highest priority, the REQ jack should be connected to the Grant-IN jack on the Event Handler; Grant-OUT should then be cabled to Grant-IN of the next-highest priority device, and so on. Grant-IN and Grant-OUT have been specially deglitched to reduce the possibility of spurious grants being transmitted or recognized. In addition, the Event Handler Auxiliary Grant-IN/Grant-OUT circuitry has been arranged such that Grant-IN will be regenerated should the Event Handler accidentally miss the initial Grant-IN. Page 7 When an L2 serial crate controller is used, the Event Handler still requires that its REQ is connected to its Grant-IN. If several auxiliary controllers are used with the L2 controller, the R/G priorities may be arranged as desired. In that case the Event Handler will honor both the ACL protocol and the R/G protocol. Note that the Event Handler honors ACL* only at the beginning of a request. If the lockout signal appears after the Grant-IN has been accepted, the Event Handler will complete that particular CAMAC transaction -- it does not abort the cycle and redo it later! Potential dataway conflicts should arise only for byte-serial operation at 5 MHz when the minimum number of idle bytes have been specified for the serial highway. The DB-25P connector on the back panel has been wired such that it is compatible with an A2-controller 40 pin ribbon connector if the DB-25S connector is offset on the 40-pin ribbon cable. The use of ribbon cables should make it easier to daisy-chain the auxiliary crate controller cable when multiple auxiliary crate controllers (multiple Event Handlers?) are used in the crate. Page 8 Event Handler BUSY Special consideration went into the design of the BUSY circuit for the Event Handler, so that, if used in the way intended, an experimenter could obtain easily a good measure of the data acquisition deadtime. There are 4 separate inputs to BUSY, each covering a different aspect of deadtime. EVENT --->|--\ | \ WAIT ---->| \ | OR )---> BUSY STOP ---->| / | / HOLD ---->|--/ The first, and most direct for the experimenter, is EVENT, the output of the Event Latch. This may be set by the front edge of the EVENT signal (front panel) or by the SETB command in software. It can be reset only by the CLRB command. The schematic Event Latch is shown directly below. SETB EVENT LATCH | ----V---- | set | +|D Q|----> EVENT | | Event Trigger --->|clk | | | | | | reset | ----^---- | CLRB When Event Trigger starts an event, and the Event Handler BUSY is used to hold off (veto) further triggers, then the Event Handler BUSY accurately reflects the system deadtime. The BUSY signal could be used to inhibit a scaler to give a "live" scaler. The CLRB operation has been implemented such that the Event Latch reset signal is gone before a subsequent Event Trigger can come in. Consequently, if the BUSY is used as an Event Trigger veto, the Event Latch is always available whenever a new event starts. Page 9 Intervention by the host computer is implemented through the PAUSE and HALT bits brought in through the FIFO output. (This assumes that one is using an appropriately modified FIFO. Directions for modifying a Kinetic Systems FIFO are given in another section.) PAUSE and HALT are combined with other signals to produce WAIT and STOP as shown in the diagrams below: PAUSE ----->|---\ HALT ----->|---\ | \ | \ 3/4 FULL -->| OR )---> WAIT RESET ---->| OR )---> STOP | / | / XPAUSE ---->|---/ XHALT----->|---/ WAIT, STOP, and EVENT are flags internal to the Event Handler and can be checked by the Event Handler so that appropriate action can be taken. WAIT is intended to be implemented such that whenever the condition appears the Event Handler will not start another event, though it will complete any event in progress. WAIT simply generates BUSY and requests a pause between events. STOP is intended to indicate that no more events are to be processed and that the Event Handler should go into a special waiting phase. In particular, when STOP goes away, it is recommended that the Event Handler perform any system reset before it removes BUSY and begins data acquisition. It is good to reload any programmable ADC gains or thresholds, to clear and reset any acquisition modules which may need it, etc. Routine use of the Event Handler in this way will remove the occasional bug that appears when a programmable module spontaneously changes its program in the middle of a data acquisition run. STOP the run to change angles or tapes or whatever, and start up totally fresh. XPAUSE and XHALT are PAUSE and HALT handled in a cascaded pair of FIFOs. They are discussed in the FIFO modification section. The RESET part of STOP refers to the front panel reset button. This button asserts STOP, hence BUSY, it clears the front panel outputs, and it clears the Event Handler Master Latch (i.e., attempts to put the Event Handler offline). HOLD is a front panel input coupled directly to BUSY, bypassing the Event Handler processor entirely. If one wants, it is possible to assert BUSY with an input. This might be used to hold off acquisition while a sample was moved or while a filling system was on. Normally it is preferable to use one of the testable front panel inputs of the Event Handler and handle the situation in software, but this direct feature is available. Page 10 Finally, there is a 3/4 FULL input (or PART-FULL) input from the FIFO which indicates that it is at least 3/4 full. This dynamic indicator in the data flow reflects the state of the host computer. Especially for systems employing a DMA transfer of data out of the FIFO, the FIFO buffer should never have more than a few data words in it, if the DMA channel is enabled. Whenever the 3/4 full condition is reached, it is a clear indication that the host computer is falling behind -- it has not yet enabled a new DMA buffer. The philosophy behind the Event Handler is that there is no reason to continue data acquisition if there is no place for the data to go. So, if the WAIT condition is detected in software, pause between events until the host catches up. In systems employing sample/hold circuits, it would be possible for the Event Handler to be held up (when the FIFO went full) in the middle of servicing these devices, and the stored signals could droop before they got processed. In fact, there is good reason not to run into the FULL condition of the FIFO, since the Event Handler will occasionally have a word lost when it interacts with a totally full FIFO. Note that, even though the Event Handler goes into a dead state whenever it attempts to output two words to a full FIFO, the BUSY signal will be correct. However, it is strongly recommended that the FULL condition be avoided by using the WAIT indication, if at all possible, and waiting near the 3/4 full point. CAMAC CRATE INHIBIT The INHIBIT line of the CAMAC crate should be avoided unless you absolutely know what you are doing. The Event Handler ignores INHIBIT -- it is unable to sense it or to drive it. Consequently the Event Handler will keep on trucking even though you have asserted INHIBIT. On the other hand, many ADCs and scalers honor INHIBIT, so you may get a very mixed bag of data acquisition if you use the INHIBIT line. If your crate controller asserts INHIBIT on power up, be certain that you do the required operation to clear this condition. Page 11 EVENT HANDLER FIFO FRONT PANEL CONNECTOR PIN-OUTS The FIFO (First In First Out) connector on the front panel of the Event Handle is a 40-pin ribbon cable header. The pin-outs for the connector are defined as shown in the following diagram. Note that the numbering does not correspond to the normal ribbon numbering convertion. A table is included which lists the pin-outs from the Event Handler internally through a ribbon cable on into a Kinetic Systems 3841 FIFO. Front Panel FIFO Connector Schematic Out-01 O1 O Out-20 Out-02 O O Out-21 Out-03 O O Out-22 Out-04 O O Out-23 Out-05 O O Out-24 Out-06 O O GND Out-07 O O Shift In* Out-08 O I Receiver Available* Out-09 O * Out-10 O I 3/4 Full* Out-11 O I xPause* Out-12 O I Pause* Out-13 O * Out-14 O I xHalt* Out-15 O I Halt* Out-16 O * Out-17 O * Out-18 O O GND Out-19 O * * 21* The letter 'O' at a pin location indicates that that pin is driven by the Event Handler; the letter 'I' indicates that the pin is to be driven by the downstream FIFO. A symbol followed by '*' is considered to be "low- true". Out 1-24 are the 24 data bits generated by the Event Handler. They are high-true levels coming directly from an LS-TTL register. GND is the system ground. Shift-In* is a low-true 200 ns pulse which signals the downstream FIFO to shift in the current data. The data will be valid for at least 200 ns before this signal is generated. In all cases, the data will remain valid until the next output is being prepared -- in the worst case the data will remain valid for at least 200 ns after the strobe. Page 12 Receiver-Available* is a signal or level from the downstream FIFO which indicates that the FIFO is ready to shift in the next word. The receiver has, typically, no more than 300 ns from the beginning of the Shift-In pulse to indicate that it is not available. From the time that the receiver goes available, there is a minimum of 100 ns before Shift-In will be asserted -- this is only when the Event Handler is waiting on the FIFO to allow the next transmission. In the most demanding case, the Event Handler can output a word to the FIFO every 500 ns, but since most reasonable data are associated with CAMAC transactions, a typical fast time of 2 micro-sec per word is much more usual. Provisions have been made so that the Event Handler can recognize two different conditions of the downstream data flow, if the relevant signals are provided by the FIFO. The Kinetic Systems 3841 FIFO includes a 3/4- FULL* (the PRT-FULL condition can be strapped to 1/4, 1/2, or 3/4 full) signal back out its input connector. The Event Handler can sense this condition in software to determine when it should hold off on data transmission. The philosophy is that there is no good reason to continue to acquire and attempt to transmit data when the host computer is unable to keep up with the data stream. In fact there are good reasons to avoid this condition, whenever possible. The worst case occurs when the Event Handler continues to fill the FIFO and a FIFO "FULL" condition occurs. When the Event Handler attempts to transmit the next word, it will hang up and be inoperative until the FIFO is able to accept another input. (A major annoyance is that the FIFO may, in fact, ignore this next word and wait for the one after it. Data may be lost if the FIFO is allowed to become full!) If the Event Handler has been programmed to monitor experimental conditions (vacuum interlocks, power supply status, user request, etc.), it will not be able to respond until the FIFO begins to empty. If electronics using sample/hold circuits are not serviced in a timely manner, their information may be corrupted. For these reasons, it is recommended that the Event Handler check the 3/4-FULL condition at the end of an event and not re-enable the data acquisition system until the FIFO is less than 3/4 full. In addition, the Event handler has been designed to interact with a modified K.S. FIFO. These modifications provide for "PAUSE" and "HALT" signals which are under program control of the host computer. (These bits can be set with an F(17)A(0) write command. The modifications are described in another section.) PAUSE and 3/4-FULL are ORed together in the Event Handler to produce the "WAIT" condition. "HALT" and manual RESET are ORed to produce "STOP". Whenever an experimenter desires to stop and change the experiment (to change angle, energy, magnetic tape, etc.), the host data acquisition program should assert the PAUSE bit. The Event Hanlder, upon sensing that WAIT is now true, should cease accepting and transmitting events. This allows the host computer time to flush the final FIFO buffer. Then the data acquisition system can set both the PAUSE and HALT bits. Upon sensing this (STOP and WAIT are true), the Event handler should hold the front-end data acquisition system busy, inhibit any triggers, inhibit any scalers, and wait for STOP to become false. Page 13 It is recommended that the Event Handler perform system initializing anytime STOP goes true and then false. After a CAMAC crate is powered on, the PAUSE and WAIT bits in the FIFO will be in ther true states, and the hardware may require special initializing. Acquisition modules (ADC, TDC, Gated Latches, etc.) may require a "CLEAR" command, a "LAM Disable" command, a conversion-gain setting command, etc. after power on. And occasionally a programmable module may lose its progamming (an innocent power surge, a collegue hits a reset button). Myriads of problems will disappear if one has the Event Handler routinely re-initialize the data acquisition system after every stop. The role of 3/4 FULL, PAUSE, and HALT in the system busy and inhibit will be discussed in the section on BUSY. Page 14 EVENT HANDLER DOWNLOADING When this Event Handler is disabled, it may be treated as a simple memory module. Note that it cannot be disabled unless the LOCK switch is down. The following CAMAC functions then apply, not to the Event Handler, but to whichever AUX you choose to communicate with: F(0) A(0) Read a 24-bit word from memory F(0) A(1) Read the 11-bit address -- bits 12-24 are not valid. F(16) A(0) Write a 24-bit word to memory F(16) A(1) Write the 11-bit address (bits 12-24 are ignored) F(24) A(0,1) Reset the local Event Handler enable latch F(26) A(0,1) Set local Enable Latch -- Enable the Event Handler! Crate Z or Reset all Enable Latches, reset front panel outputs RESET button When the Event Handler is enabled, all functions except for F(24) should receive a "NO Q" response. That is, when the Event Handler is enabled, you are not permitted to talk to it. All communicating with the Event Handler is performed via front panel inputs or via the FIFO module. If the LOCK switch is down, the F(24) function should disable the Event Handler and receive a normal Q response. The exception to this is when the Enable Latch is set in the other AUX. Then one must do an F(24) to the other AUX or push the RESET button. While the Event Handler is disabled, all of the above functions should receive the normal Q response, including the F(26) function. WHICH SLOT IS THE RIGHT ONE? When you want to address the Event Handler, remember that the communication can be through either AUX (in a double AUX setup). For a single AUX system, the active slot for the Event Handler is the right hand one of the double wide module -- the left hand slot is for the processor, and it uses the dataway simply for power. The following is a straightforward way to download a PROGRAM of N 24- bit words into the Event Handler, beginning at address = 0. This assumes that you have a subroutine CNAF(C,N,A,F,Q,DATA) which will perform a CAMAC function F to module N at subaddress A in CAMAC crate C, where DATA is a 24- bit I/O word, and Q is the response. Page 15 C SAMPLE "FORTRAN" PROGRAM TO DOWNLOAD THE EVENT HANDLER INTEGER PROGRAM(2048), AUX, Q, C, ERROR DATA AUX / 23 / ;AUX SLOT # DATA C / 1 / ;CRATE # CALL CNAF(C,AUX,0,24,Q,I) ;disable Event Handler IF(.NOT.Q) THEN WRITE "Unable to clear the Event Handler. Check the LOCK switch, RESET, and try again!" STOP END IF C --- DOWNLOAD THE PROGRAM --- DO 10 I=1,N CALL CNAF(C,AUX,1,16,Q,I-1) ;write address IF(.NOT.Q) THEN 5 WRITE "Trouble while talking to the Event Handler. Check for problems, and try again?" STOP END IF CALL CNAF(C,AUX,0,16,Q,PROGRAM(I)) ;write 24-bit instruction IF(.NOT.Q) GOTO 5 10 CONTINUE C --- NOW, VERIFY IT --- ERROR = 0 DO 20 I=1,N CALL CNAF(C,AUX,1,16,Q,I-1) ;write the address again IF(.NOT.Q) GOTO 5 CALL CNAF(C,AUX,0,0,Q,J) ;read the memory IF(.NOT.Q) GOTO 5 IF(J .NE. PROGRAM(I)) THEN WRITE (15) I-1, PROGRAM(I), J 15 FORMAT(I5, 2Z10) ;print out error, in hex ERROR = ERROR + 1 END IF 20 CONTINUE C --- DID I DO IT? --- IF(ERROR .GT. 0) THEN WRITE (25) ERROR 25 FORMAT (5X 'ENCOUNTERED' I5, ' ERRORS. TRY A CAB NEXT TIME.') STOP ELSE WRITE "NO MEMORY ERRORS ENCOUNTERED" END IF C --- TURN THE EVENT HANDLER ON --- CALL CNAF(C,AUX,1,16,Q,0) ;set address=0 IF(.NOT.Q) GOTO 5 CALL CNAF(C,AUX,0,26,Q,I) ;turn if on IF(.NOT.Q) GOTO 5 ;should like being turned on? CALL CNAF(C,AUX,0,26,Q,I) ;try a second turn-on IF(Q) THEN WRITE "EVENT HANDLER DID'T TURN ON AS EXPECTED! PLEASE CHECK IT OUT" STOP ELSE WRITE "EVENT HANDLER LOADED AND ENABLED. GOOD LUCK" STOP END Page 16 EVENT HANDLER REGISTER ROAD MAP o--------------------o | 24 bit Program Reg | o------------< | (#) | >---o | o--------------------o OUT # Xmit 16 bits | V | | MOV #,CA MOV #,TXR | | MERG # Xmit 16 bits | 16 bits 16 bits | | 13-16 replaced | don't Xmit | | 1-12 unchanged | | | V | V o-------o | o-------o C | | >---o MOV UCA,CA o--> | | A | A R | | 8 MSB->8 LSB | |F o------o M | U E | <---o 0's--> 9-16 | X |R | | A | X C G | | M |O | E F | C | I A I | OUT CA 24 bits | I |N C --\ | X | NAF | L M S | OUT UCA | T |T A ---\ | T I | <----> | I A T | 8 MSB-->8 LSB; 0's-->9-16 | | B ----> | E | CNAF | A C E | ----------------------------> | R |P L ---/ | R F | D | R R | MOV CA,TXR 24 bits | E |A E --/ | N | A | Y | don't Xmit | G |N | A O | T | | | |E | L | A | (CA) | | (TXR) |L | | W | (CA1) | --> MOV CA,PAT --o | | o------o A | (CA2) | | o---> | | Y | | <-- MOV PAT,CA | | o-------o o-------o ^ | | SKIP CA.NONE.# | | | SKIP CA.ANY.# | | | SKIP CA.LT.# | | | OUT PAT Xmit 16 bits SKIP CA.GT.# | | | Test 16 LSB | | | ^ v ^ o--------------------o SKIP PAT.NONE.# | 24 bit Pattern Reg | --- SKIP PAT.ANY.# | (PAT) | --- SKIP PAT.LT.# o--------------------o SKIP PAT.GT.# SKIP UPAT.ANY.# Test 16 LSB SKIP UPAT.NONE.# Test 8 MSB Page 17 EVENT HANDLER EXTERNAL REGISTER --(EX)-- --(EX1)-- --(EX2)-- ------ (input) ------- ------ (output) ------ [1] LS-TTL [1] 50 ohm [2] LS-TTL [2] 50 ohm [3] LS-TTL 8 [3] 50 ohm 8 [4] LS-TTL front [4] TTL front [5] LS-TTL panel [5] TTL panel [6] LS-TTL inputs [6] TTL outputs [7] NIM [7] NIM [8] NIM [8] NIM ----- (8 status flags) ---------------------- [ 9] GOOD Q (Aux 1 or 2) LOAD # (absolute set/clear) [10] EVENT (Event Latch) [11] WAIT (FIFO) --selectively-- [12] STOP (FIFO) SSET # (set) [13] NAF BUSY (Aux 1 or 2) SCLR # (clear) [14] OUT BUSY (FIFO) SCMP # (complement) [15] Output #4 (# = 8 bit byte) [16] Output #5 ---------------------- SKIP EX.ANY.# Test 16 bits SKIP EX.NONE.# Page 18 EVENT HANDLER BASIC INSTRUCTION LIST (BIT PATTERN) |2222|2111|1111|111 | | | |4321|0987|6543|2109|8765|4321| Representation (HEX) ---------------- |----|----|----|----|----|----| -------------------- NOP |0000|0000| | | | | 0 1) CAMAC Operations CNAF C,N,A,F |X001|0000|00NN|NNNA|AAAF|FFFF| 100000+N,A,F X=C-1 | | | | | | | NAF N,A,F |0001|0000|00NN|NNNA|AAAF|FFFF| 100000+N,A,F | | | | | | | NAF (P),N,A,F |0001|1000|00NN|NNNA|AAAF|FFFF| 180000+N,A,F | | | | | | | NAF (S),N,A,F |0001|0000|01NN|NNNA|AAAF|FFFF| 104000+N,A,F | | | | | | | NAF (N),N,A,F |0001|0000|10NN|NNNA|AAAF|FFFF| 108000+N,A,F | | | | | | | NAF (PS),N,A,F |0001|1000|01NN|NNNA|AAAF|FFFF| 184000+N,A,F | | | | | | | NAF (PN),N,A,F |0001|1000|10NN|NNNA|AAAF|FFFF| 188000+N,A,F Branch Instructions BRU A |0010|0101|0 | AAA|AAAA|AAAA| 250000+A | | | | | | | BRUR |0010|0000|0 | | | | 200000 | | | | | | | SPB A |0010|1101|0 | AAA|AAAA|AAAA| 2D0000+A | | | | | | | SPBR |0010|1000|0 | | | | 280000 | | | | | | | INTE A |0010|1111|0 | AAA|AAAA|AAAA| 2F0000+A | | | | | | | INTR |0010|1010|0 | | | | 2A0000 | | | | | | | 2) BSPE |0010|1001|1 | | | | 298000 Unsupported Delay for #*100ns DLAY # |0110|0000| |@@@@|@@@@|@@@@| 60F000+@ @=4095-# 8 Front Panel Outputs SSET b |0100|0011|1111|1111|bbbb|bbbb| 43FF00+b b=8 bit byte | | | | | | | LOAD b |0100|0011|BBBB|BBBB|bbbb|bbbb| 430000+256*b+b | | | | | | | SCLR b |0100|0011|$$$$|$$$$|0000|0000| 430000+256*$ $=complement(b) | | | | | | | SCMP b |0100|0011|$$$$|$$$$|bbbb|bbbb| 430000+256*$+b Page 19 BASIC INSTRUCTION LIST (BIT PATTERN) (CONTINUED) |2222|2111|1111|111 | | | |4321|0987|6543|2109|8765|4321| Representation (HEX) ---------------- |----|----|----|----|----|----| ---------------------- CLRB |0111|0000| | | | | 700000 | | | | | | | SETB |0111|0001| | | | | 710000 Bit Checking SKIP PAT.ANY.# |0011|0000|####|####|####|####| 300000+# | | | | | | | SKIP UPAT.ANY.b |0011|0001|0000|0000|bbbb|bbbb| 310000+b (8 bits) 3,4) | | | | | | | SKIP EXX.ANY.# |X011|0010|####|####|####|####| 320000+# 3) | | | | | | | SKIP CAX.ANY.# |X011|0011|####|####|####|####| 330000+# | | | | | | | SKIP PAT.NONE.# |0011|0100|####|####|####|####| 340000+# | | | | | | | SKIP UPAT.NONE.b |0011|0101|0000|0000|bbbb|bbbb| 350000+b (8 bits) | | | | | | | SKIP EXX.NONE.# |X011|0110|####|####|####|####| 360000+# | | | | | | | SKIP CAX.NONE.# |X011|0111|####|####|####|####| 370000+# Arithmetic Compares (16 bits) SKIP CAX.LT.# |0011|1011|####|####|####|####| 3B0000+# | | | | | | | SKIP CAX.GT.# |0011|1111|####|####|####|####| 3F0000+# | | | | | | | SKIP PAT.LT.# |0011|1000|####|####|####|####| 380000+# | | | | | | | SKIP PAT.GT.# |0011|1100|####|####|####|####| 3C0000+# Move Source to Destination MOV #,CAX |X100|0000|####|####|####|####| 400000+# | | | | | | | MOV CAX,PAT |X100|0001| | | | | 410000 | | | | | | | MOV PAT,CAX |X100|0010|0 | | | | 420000 | | | | | | | MOV UCAX,CAX |X100|0010|1 | | | | 428000 | | | | | | | MOV #,TXR |0101|0000|####|####|####|####| 500000+# don't xmit | | | | | | | MOV CAX,TXR |X101|0001| | | | | 510000 don't xmit Page 20 BASIC INSTRUCTION LIST (BIT PATTERN) (CONTINUED) |2222|2111|1111|111 | | | |4321|0987|6543|2109|8765|4321| Representation (HEX) ---------------- |----|----|----|----|----|----| ---------------------- 5) Transmit the Source to FIFO MERG # |0101|1100|####|----|----|----| 5C0000+# xmit | | | | | | | OUT # |0101|1000|####|####|####|####| 580000+# | | | | | | | OUT CAX |X101|1001| | | | | 590000 (24 bits) | | | | | | | OUT PAT |0101|1010| | | | | 5A0000 (16 bits) | | | | | | | OUT UCAX |X101|1010|1 | | | | 5A8000 (8 bits) | | | | | | | 2) OUT SPEC |0101|1011| | | | | 5B0000 Unsupported Page 21 BASIC INSTRUCTION LIST NOTES 1) CNAF takes same forms as NAF except that C must be given in order to select the desired Auxiliary Crate Controller (AUX). NAF assumes that C=1, bit 24 = 0, first AUX selected. 2) Unsupported refers to the possibility of adding a special board to the Event Handler to implement a special BRANCH and special OUT instruction. For a discussion of "Branch to First Significant Bit," see| D. C. Hensley, "The Event Handler II, A Fast, Programmable, CAMAC- Coupled Data Acquistion Interface, IEEE Trans. Nucl. Sci. NS-26, No. 4, 4454-4458 (August 1979) 3) CAX denotes: CA, CA1, CA2 (CA is same as CA1) EXX denotes: EX, EX1, EX2 (EX is same as EX1) EX2, CA2, or C=2 result in bit 24 being set --> 2nd AUX. X denotes where bit 24 might be set. 4) The (EX) register contains the status of "Q" and "NAF Busy" for the AUX of interest. Specifiying (EX2) allows one to check these bits for the 2nd Aux. See the Register Roadmap Section for a complete listing of the (EX) register. Examples: SKIP EX2.NONE.[9] Check "Q" (For 2nd AUX) SKIP EX2.ANY.[13] Check "NAF Busy" 5) MERG # transmits lower 12 bits unchanged, upper 12 bits are changed. In particular, bits 13-16 are specified by bits 13-16 of #. Page 22 EVENT HANDLER Basic instruction List -- Instruction -- --- Discussion --- NOP NO-OP No operation -- a 400 ns interval. SETB Set Event Latch -- forces front panel (FP) BUSY CLRB Clear Event Latch -- may release (FP) BUSY output ---Front Panel Outputs--- SSET # / set the indicated output on SCLR # Selectively -- clear the indicated outputs SCMP # \ complement the indicated outputs LOAD # Load # into outputs: indicated outputs are set, non-indicated outputs are cleared. CAMAC I/O is to/from the Auxiliary Camac Register (CA) N=module slot # A=sub-address in module F=CAMAC funtion # NAF N,A,F Execute NAF (data to/from CA1 implied) CNAF C,N,A,F C=1,2 -- data to/from CA1 or CA2 NAF (P),N,A,F Start NAF and proceed immediately to next instruction CNAF (P),C,N,A,F NAF (S),N,A,F NAF with a short CAMAC cycle CNAF (S),C,N,A,F (No S2 and quit after S1) NAF (N),N,A,F NAF with a short/quiet CAMAC cycle CNAF (N),C,N,A,F (No S1 or S2, quit after S1) NAF (PS),N,A,F Start a short NAF and proceed NAF (PN),N,A,F Start a short/quiet NAF and proceed CNAF (PN),C,N,A,F MOV CA,PAT Copy contents of CA to Pattern Reg (PAT) MOV CA1,PAT MOV CA2,PAT MOV PAT,CA Copy contents of PAT to CA (16 LSB) MOV PAT,CA1 MOV PAT,CA2 MOV CA,TXR Copy contents of CA to Transmit Reg (TXR) MOV UCA,CA Copy 8 MSB to 8 LSB; (0's to bits 9-16) MOV UCA1,CA1 MOV UCA2,CA2 MOV #,TXR Copy # to TXR (16 bits) MOV #,CA COPY # to CA (16 bits) MOV #,CA1 or CA2 OUT = Copy source to TXR register and Transmit to FIFO OUT CA Xmit CA OUT CA1 or CA2 OUT # Xmit # OUT UCA Move 8 MSB to 8 LSB of TXR & Xmit; bits 9-16=0 OUT UCA1 or CA2 OUT PAT Move 16 LSB of PAT to TXR & Xmit OUT SPEC Special OUT, not yet supported MERG # Move bits 13-16 of # to bits 13-16 of TXR & Xmit (bits 1-12 unchanged) Page 23 EVENT HANDLER Basic Instruction List (continued) SKIP: Skip next instruction if condition satisfied! SKIP EX.ANY.# SKIP EX1.ANY.# condition true if any bits of EX and # match SKIP EX2.ANY.# SKIP CA.ANY.# SKIP CA1.ANY.# SKIP CA2.ANY.# SKIP PAT.ANY.# SKIP UPAT.ANY.# (8 bits only) SKIP EX.NONE.# condition true if no bits of EX and # match SKIP EX1.NONE.# SKIP EX2.NONE.# SKIP CA.NONE.# SKIP CA1.NONE.# SKIP CA2.NONE.# SKIP PAT.NONE.# SKIP UPAT.NONE.# (8 bits only) SKIP CA.LT.# condition true if CA < # (16 bits) SKIP CA1.LT.# SKIP CA2.LT.# SKIP PAT.LT.# SKIP CA.GT.# condition true if CA > # (16 bits) SKIP CA1.GT.# SKIP CA2.GT.# SKIP PAT.GT.# BRU DEST Unconditional Branch to Destination DESTination may be of form: # @+# @-# NAME NAME+# NAME-# (where @ refers to current location) SPB DEST SPB = Store Position and Branch -- Similar to CALL in Fortran. DEST same form as for BRU. BRUR Return from subroutine SPBR Store current position and return INTE DEST Same as SPB, but sets Interrupt Enable. Externally generated Interrupt will then cause a SPB + BRUR (SPBR) to be executed. INTR Return from Interrupt; Re-enable interrupt BSPE Special branch, not yet supported DLAY # Wait for #*(100 ns), up to 409.6 micro-sec Page 24 EVENT HANDLER DISCUSSION OF INTERRUPTS The Event Handler has been provided with an interrupt capability, if you should have the nerve to use it. It will allow you to reach a service routine within about 1 micro-sec, if you need to, but there are some things to consider. First, the interrupt uses the single stack for its interrupt vector. This is the same stack that is used in the one-deep subroutine call capability of the Event Handler. Consequently, any "CALL" (SPB or SPBR) will distroy the interrupt vector (and disable the interrupt). The good news is that this is the way to temporarily disable the interrupt while performing an un-interruptable operation. An interrupt request coming in during this disable time will be serviced as soon as the interrupt is re- enabled. Next, an interrupt is compatible with all operations, except DELAY. The DELAY operation is interrupted immediately, all other operations finish before the interrupt is honored. Finally, there is no special provision for saving the "background" context while servicing an interrupt. That is, you should not use the PAT register or the CAMAC registers unless you know the background task will not be hurt by your changing them. You could use one crate for background and one crate for interrupt, if you chose. Fortunately, the front panel outputs can be selectively manipulated, so you can generate selected outputs without affecting the background condition of the remainder of thefront panel. When an interrupt occurs, the address of the next sequential instruction is saved (for a return) and the first instruction of the interrupt processing procedure is executed. The interrupt capability is disabled by an interrupt. The next instruction executed after the INTR instruction is the appropriate next instruction at the time of the interrupt. HOW TO CLEAR AN UNWANTED INTERRUPT INTE NEXT Allow interrupt -- if there, it will vector to NEXT. NEXT SPB NEXT1 Disable interrupt NEXT1 -- Continue with your program ^ |--- indicates any Event Handler operation Page 25 HOW TO USE IT LOOP -- -- SPB SETUP Go set up the interrupt, i.e., go to SETUP, enable interrupt, define place to go when an interrupt is received (namely: INTX), and return. -- SPB @+1 Turn off interrupt for critical step (Interrupt will be saved.) -- SPB SETUP Go set up interrupt again -- -- XX ROUT N,A,F Random operation at which interrupt is assumed to occur -- -- BRU LOOP * * * * * The INTR operation enables the interrupt, stores the address of the next instruction as the interrupt vector, and returns, either from an interrupt or from an SPB call to SETUP. SETUP INTR INTX -- Interrupt vectors to here! -- -- Interrupt service routine -- -- BRU SETUP Set up interrupt again and return to the program at the point at which it was interrupted (at XX+1, in this example!) Page 26 EVENT HANDLER PROGRAMMING HINTS This is intended as a discussion of the general way the Event Handler was intended to be used. You may come up with better ways to do things, or you may have needs that are totally different from those addressed here, but it is hoped that this will enable you to get trustworthy performance from the Event Handler. For this, I am assuming that you are working with a modified FIFO that passes both PAUSE and HALT along with 3/4 FULL back through the FIFO output on the Event Handler. I will assume that you are making use of the BUSY output of the Event Handler to generate the system deadtime signal -- this implies that you are initiating an event with an Event Trigger which you are presenting to the Event Handler at the EVENT input, and, I hope, you are using the BUSY output to veto/inhibit the Event Trigger generator. The program has the following general flow: 1) Halt handling section -- Beginning section Hang on Stop 2) Module/system initialize 3) Clear the system 4) Hang until Event or Wait or Stop Wait -->6 Stop -->1 Event-->5 5) Process the Event 6) Set Busy, hang if Wait or Stop Stop-->1 Wait-->6 Nothing-->3 Lets apply this format to a simple example and see what we get. Suppose we have 2 uncorrelated detectors each of which has a time reference with respect to something (the RF?). I will use fast ADCs for the energies, but assume that the TDC module is slow, 100 micro-s. To simplify things, I found a gated latch and have assigned a bit to each detector. I found that I was writing too much junk on tape, so I set a threshold requirement on the ADCs, and even though it is overkill in this case, I have decided to index the flow to allow for a sparse data scan. 8000h+1 is the index for the first detector and TDC, 8000h+3 is the index for the 2nd detector and TDC. 8000h sets the 16th bit as a flag. Page 27 *-*-*-*-* Definitions of bits, modules, inputs, outputs, etc. *-*-*-*-* EVENT=10 ;bit position of Event Latch WAIT=11 STOP=12 ; MODULE SLOT #s -- USING ONLY CRATE #1 GL=5 ;gated latch slot FADC1=1 ;slot position of fast ADC module FADC2=2 TDC=3 ;time digitizer ; FRONT PANEL INPUTS TDCB=2 ;TDC busy* signal (low true) ; FRONT PANEL OUTPUTS INHIBIT=7 ;50 ohm NIM output to scalers CLEAR=8 ;clear pulse ; CONSTANTS THRESHOLD=99 ;threshold value for good ADC *-*-*-*-* 1) Beginning section *-*-*-*-* *-*-*-*-* Halt handling section *-*-*-*-* I start out by making the system busy (SETB) and I also generate an inhibit for scalers. This inhibit is different from the system BUSY. I find that I like to have some scalers free run, such as the integrator, the clock, and various rates that I don't want affected by deadtime -- but most of them I don't want to continue accumulating after I have stopped the acquisition. Hence, I use a separate inhibit for those scalers. Any scaler inhibited by the BUSY will respond directly to the stop. HALT SETB LOAD [INHIBIT] HL SKIP EX.NONE.[WAIT,STOP] ;wait until they go away BRU HL LOAD 0 ;clear front panel *-*-*-*-* 2) Module/system initialize *-*-*-*-* I need to program my fast ADCs, but there is nothing to initialize with the TDC or Gated Latch. Note that this section is not concerned with clearing -- only initializing! SET MOV 100H,CA NAF FADC1,0,17 ;programmable gain --> 100h NAF FADC2,0,17 *-*-*-*-* 3) Clear the system *-*-*-*-* This is the section which will clear modules. If at all possible, I will have the modules cleared by the pulse associated with the CLEAR output. This is best, because one operation clears everyone, but some modules (the fast ones!) can often only be cleared via the dataway (the slow way). Sigh. CLER SSET [CLEAR] ;this pulse clears TDC & GL SCLR [CLEAR] NAF FADC1,0,9 ;clear fast ADC NAF FADC2,0,9 Page 28 *-*-*-*-* 4) Hang until Event or Wait or Stop *-*-*-*-* Notice that in this straighforward application, the system is ready to go as soon as I release the Event Latch, hence BUSY. Then I will hang in a wait loop, testing EVENT, WAIT, and STOP. As soon as one of these becomes true, I will respond. WAIT --> set BUSY, and wait. STOP --> set BUSY and INHIBIT and wait. EVENT --> process it. CLRB EL SKIP EX.ANY.[EVENT,WAIT,STOP] BRU EL SKIP EX.NONE.[WAIT,STOP] ;pause, if either BRU PAWS SKIP EX.ANY.[EVENT] ;check for glitches BRU EL *-*-*-*-* 5) Process the Event *-*-*-*-* The first thing I do here is get hold of my gated latch, since it is an immediately ready module. I should have a bit set, if not, I'll crash the event. There is no waste of time doing this since I have to wait for the fast ADCs, anyway. NAF GL,0,0 MOV CA,PAT SKIP PAT.ANY.[1,2] ;either detector there? BRU CLER ;no Normally I would have a signal here to check to find out when the fast ADCs were ready. Unfortunately they mostly don't have a front panel output that tells you very much. Be careful about checking them on the dataway, sometimes a "smart" ADC that doesn't see an input above threshold is never ready. In this section I am simply checking the ADCs to see that at least one is above threshold, if not, I will crash it. Again, no time is wasted since the TDCs are still working away. DLAY 100 ;wait 10 micro-s for ADC SKIP PAT.ANY.[1] BRU CK2 NAF FADC1,0,0 SKIP CA.LT.THRESHOLD+1 BRU GOOD CK2 SKIP PAT.ANY.[2] BRU CLER NAF FADC2,0,0 SKIP CA.GT.THRESHOLD BRU CLER At least one of the ADCs was valid, so I will now wait for the TDC. Note that the busy signal is low true. Also note that it is impossible to hang forever on this signal -- the TDC will always go non-busy. Be careful of hanging on a condition that may never change. GOOD SKIP EX.ANY.[TDCB] ;wait for TDC (low true check) BRU GOOD Page 29 Just to keep things clean, I will again check the threshold before shipping the event. I know that at least one is above threshold, and it will cost me only 1 micro-s to check it out, so I will. Note that the index is shipped before the ADC,TDC. SKIP PAT.ANY.[1] BRU T2 NAF FADC1,0,0 SKIP CA.GT.THRESHOLD BRU T2 OUT 8001H ;index for detector #1 OUT CA ;out the ADC NAF TDC,0,0 ;TDC #1 OUT CA T2 SKIP PAT.ANY.[2] BRU EOE NAF FADC2,0,0 SKIP CA.GT.THRESHOLD BRU EOE OUT 8003H ;index for detector #2 OUT CA NAF TDC,1,0 ;TDC #2 OUT CA This is the event separator. For this simple system one could get away without it, but as soon as there are more parameters, or if the parameters don't always come in sequential order, you need to have a re-syncing word. EOE OUT 0FFFFH ;End Of Event -- event separator *-*-*-*-* 6) Set Busy, hang if Wait or Stop *-*-*-*-* This is where I come, if I see the WAIT bit on. If it is simply the end of the event, the SETB command is redundant, but it saved me some duplicate code if I put it here. Note that I do not free up the system for another event unless the FIFO highway is free. If I run into STOP, I will go off to assert INHIBIT and then re-initialize the system when it is time to start up again. PAWS SETB PL SKIP EX.ANY.[WAIT,STOP] BRU CLER ;go prepare for another event SKIP EX.ANY.[STOP] BRU PL ;am I still waiting? BRU HALT ;oops, time to stop! END I think you would find that the average deadtime of this application would be the conversion time of the TDC module plus about 16 micro-s. The 16 micro-s is the time to read, check, xmit, check highway, clear, and go. And some TDC modules have a screw adjustment on the BUSY -- you could cut it from 100 micro-s to 30 micro-s. (And then put it back on the shelf without telling anyone what you had done.) It is possible to speed up the Event Handler part, especially if you have many parameters, but a 20% improvement on something that is less than 20% of the deadtime anyway is not very interesting here. Page 30 EVENT HANDLER FIXING In order to fix the Event Handler or to reconfigure it, one may need to take it apart. There i a simple way to do this which may leave you with a working version when all is said and done. OPENING AN EVENT HANDLER First of all, the Event Handler processor board is permanently attached to the front panel but has no connection with the back panel. The processor board is the one on the left, when the module is viewed from the front. On the other hand, while the AUX board is permanently attached to the back panel and to the front panel, its connection to the front panel is long enough that the module can be separated and opened up, much like a succulent bivalve. Thus, remove the two screws on the back panel which hold the processor board, remove the two screws on the front panel which hold the AUX board, gently separate the two boards, and lay it open. (Only the very first model has a short tether -- some of the wires ended up shorter than intended because the wrong size wirewrap tool was used.) INSTALLING ALTERNATE RIBBON CABLES The ribbon cables connecting the two boards have been purposely made about 5 inches long so that there is room to separate the two boards, and the wires connecting the AUX to the front panel should be equally long. If you intend to replace the top ribbon cable in order to implement a dual AUX system, I recommend that the ribbon include at least 5 inches of slack between the processor board and the captive AUX. The length of the cable from there to the 2nd AUX should be kept reasonably short, but a length of 2 feet has worked with no trouble. I would worry about 10 feet since this ribbon supports the main processor bus, so be reasonable. COMPONENT REMOVAL -- SOLDER REPAIRING The Multiwire boards are not easy to repair because they have very small solder pads. It would be best to use a vacuum desoldering unit if you need to replace a chip, and you should use a very sharp tip iron with a temperature around 600 degrees F. Before replacing an apparently bad chip, examine it closely to see if perhaps one of the legs has a cold soldering problem. If you are not certain, resolder it so that the solder clearly wets through to the component side of the board. Be especially careful when working with the power or ground pins -- the thermal isolation from the ground/power planes is not overly adequate. SETTING THE AUX NUMBER The Event Handler can control up to 2 auxiliary crate controllers, but you need to set the switch so that they are distinct. The select switch for each AUX resides at the top of the AUX board, very near the front. The top switch of the double DIP switch determines the number -- flip it to change the number of the AUX. You will need to pull the Event Handler out of the CAMAC crate a few inches to be able to see and reach the switch. The fruits of your labor will then be indicated on the front panel of the module -- the AUX number is marked by an LED. The switch is in the same place on the single AUX module, just easier to reach. Page 31 REPLACING FUSES You will know you have to replace the +6V fuses in the Event Handler processor or AUX when the associated LEDs won't light. Pushing the reset button should turn on the STOP and BUSY LEDs, and the AUX select LED should always be on. The processor board has a -6V fuse which will affect its ability to generate NIM outputs or to recognize NIM inputs, although all of the TTL inputs/outputs should keep on trucking. The processor fuses are on the lower-back corner on the left hand side. These can be replaced without disassembling the Event Handler. The fuse for the AUX is in the same place on the AUX board, but you will probably have to open the module up to replace it. WHICH SLOT IS THE RIGHT ONE? When you want to address the Event Handler, remember that the communication can be through either AUX (in a double AUX set up). For a single AUX system, the active slot for the Event Handler is the right hand one of the double wide module -- the left hand slot is for the processor, and it uses the dataway simply for power. Page 32 EVENT HANDLER MODS TO OTHER MODULES Kinetic Systems 3841 256 Deep FIFO This modification is to allow the host computer to communicate up to 2 bits of information to the Event Handler. There are many levels of revision of the K.S. FIFO, so check that the chips indicated here are the correct ones for your particular module. We are going to connect write bits #13 and #14 to an LS175 4 bit register -- 2 of the bits of this register are already used. Bits #13 and #14 were chosen because they already have a buffer gate from the dataway. Chip B is a hex inverter F is an LS175 register J1 is the front panel input connector J2 is the front panel output connector connect B-04 to F-04 W13 to register #3 connect B-10 to F-13 W14 to register #4 connect F-02 to J1-45 Pause* to input connector connect F-15 to J1-46 Halt* to input connector OPTIONAL (for cascaded FIFO operation) This requires that the cable connecting the two FIFOs be pin for pin. connect J1-43 to J2-45 xPause* to Pause* of next FIFO connect J1-44 to J2-46 xHalt* to Halt* of next FIFO When Pause* and Halt* are low, they are asserted. They will be set low on a power up of the module. They can be controlled with the F(17) A(0) function. F(17) A(0) datum = 0 assert both Pause and Halt = 1000h Pause off, Halt asserted = 2000h Halt off, Pause asserted = 3000h both Pause and Halt off If cascaded FIFOs are used, you must turn Halt/Pause off in the FIFO you do not wish to control through. Then either Halt/Pause or xHalt/xPause will control the Event Handler. Note that 3/4 FULL will always be sensed in the FIFO closest to the Event Handler. Page 33 LeCroy 2228A Octal TDC The point of this modification is to provide a "module busy converting" signal to the outside world. The module has an internal clock gate which is on while the module is converting. This is buffered in a spare NAND gate and brought to the front panel. connect SL-08 to SL-04 Clock gate to buffer and to SL-05 (both inputs of NAND) connect SL-06 to Front Panel BUSY* (low true) If this output were connected to input #1 of the Event Handler, and you wished to wait for the TDC to convert before reading it: WAIT SKIP EXT.ANY.[1] ;wait for BUSY* to end BRU WAIT NAF N,A,TDC ;read TDC LeCroy 2249W 12 Channel Integrating ADC LeCroy 2259 12 Channel Peak Sensing ADC A BUSY* signal can be obtained very simply by connecting Q* of the "Converting" 1-shot to the front panel. This is a signal which is low while the module is busy converting. As soon as it goes high, you may read the ADC. connect TD-09 to front panel 9602 1-shot Q* ORTEC AD-811 Octal Peak Sensing ADC You may generate a BUSY signal from the ADC by taking the output of the BUSY 1-shot. This is a 9602 labeled 2G. connect 2G-10 to front panel BUSY or connect 2G-09 to front panel BUSY* CAUTION -- do not load this signal, as you are taking it off unbuffered and it is used elsewhere in the module. Any of the Event Handler inputs 1 to 6 do not load this signal and may be used. Page 34 MACRO INSTRUCTION LIST AND DEFINITIONS W. T. Milner Assembler Directives to the Assembler ("EQUATE", LOOP, ENDLOOP) SYM=EXPRESSION Directs assembler to evaluate EXPRESSION and assign the resulting value to SYM. LABL LOOP NLOOP Directs the assembler to "replicate" the set of statements bounded by the LOOP- and ENDLOOP-directives. Do it NLOOP times. ENDL ENDLOOP Defines End-of-Loop. ASSEMBLY-TIME VARIABLES Symbols defined by the "Equate Directive" (SYM=EXPRESSION) are called assembly time variables or just assembly variables. Such variables may be re-defined without restriction. Note: These are not run-time variables! - THERE ARE NO RUN-TIME VARIABLES! Assembly variables must always be defined in terms of numbers and/or previously defined assembly variables. Defining expressions may include "Bit-Lists". STATEMENT LABELS The label on the ENDLOOP directive as well as any other labels defined between the LOOP and ENDLOOP directives are undefined outside of the loop and may be used in other loops. All other statement labels, including those on the LOOP directive Are defined to all parts of the program and, therefore, must be unique. * * * * LABELING OF THE "EQUATE" DIRECTIVE IS NOT ALLOWED * * * * Page 35 EXPRESSIONS The assembler supports simple expressions which are evaluated left to right. REPEAT!! EVALUATED! LEFT! TO! RIGHT! Let "V" represent a single value (number or previously defined symbol). Let "S" represent an algebraic sum of "V's". Expressions of the following type are legal: A=V A=S A=S*V+S Means: A=(S)*V+S A=S/V+S Means: A=(S)/V+S A=S/V*V+S Means: A=((S)/V)*V+S A=MOD(S,S) No additional terms allowed (same argument definition as in Fortran) A=S+[S,S,..] Where [ ] encloses a list of "bits" NUMERICAL EXAMPLES: ASSIGNMENT RESULT A=10 A=10 B=A+4 B=14 C=A+B-9 C=15 D=100/B D=7 E=A+B+C/6 E=6 F=A+B-C*7 F=63 G=A+B-C/6*A G=10 H=A+B-C/6*A+C+10 H=35 I=MOD(A+B,7) I=3 J=MOD(A+B,E-1) J=4 K=[A+6,3] K=8004 (HEX) L=[A+6,3]+40H L=8044 (HEX) M=[2,1] M=3 N=[A+6,M] N=8004 (HEX) * * * PARENTHESES ARE NOT ALLOWED EXCEPT IN THE "MOD STATEMENT" * * * Page 36 SYNTAX RULES (1) All statement labels must start in col-1 and be no greater than 8 characters in length. (2) All instructions (Basic and Macro) must start after col-1. At least one blank must separate any statement label and the instruction field. (3) At least one blank must separate the instruction and operand fields. (4) embedded blanks are allowed in (but removed from) the IF-MACRO, expressions, and operand fields of all types. That is, you may type it any way you wish, but I will re-format it to be the way I like it. (5) The symbol being defined by an EQUATE may start in any column and be up to 8 characters in length. (6) All comment fields must be preceded by a semicolon (;). (7) A completely blank line will show up as a blank line in the assembly listing and otherwise be ignored. (8) All numbers are decimal by default. (9) Hex numbers are specified by a trailing "H" (8000H for example). The first character must be a decimal integer (0 to 9). (10)"Bit Expressions" are lists of bit-numbers enclosed in [ ]. Example: [16,1,2] produces 8003H. (11)Bit-Lists are not allowed in elements of a N,A,F or C,N,A,F. (12)Expressions enclosed by < > within a comment-field are evaluated and replaced by a 3-digit decimal integer in the assembly listing. This is for labeling purposes only: any errors will be ignored. * * * EXPRESSIONS ENCLOSED BY < > MAY NOT CONTAIN EMBEDDED BLANKS * * * Page 37 PROGRAMMING EXAMPLES Loops are initiated by the LOOP directive and terminated by the ENDLOOP (equivalent to CONTINUE in fortran). An example is shown below: SPAT 1,1,0 ;READ & STORE PATTERN REGISTER B=0 ;INIT PATTERN REG BIT COUNTER AA=-1 ;INIT ADC SUB-ADDR CNTR AT=-1 ;INIT TDC SUB-ADDR CNTR DET=0 ;INIT DETECTOR COUNTER ID=-2 ;INIT PARM ID # NADC=10 ;SLOT FOR ADC (ADC IN 10 & 11) NTDC1=12 ;SLOT FOR TDC1 (TDC1 IN 12 & 13) NTDC2=7 ;SLOT FOR TDC2 (TDC2 IN 7 & 9) DSA=1 ;SLOT INC FOR ADC DST1=1 ;SLOT INC FOR TDC1 DST2=2 ;SLOT INC FOR TDC2 CA=-1 ;CNTR FOR ADC SLOT SWITCHING CT1=-1 ;CNTR FOR TDC1 SLOT SWITCHING CT2=-1 ;CNTR FOR TDC2 SLOT SWITCHING LU1 LOOP 16 B=B+1 AA=MOD(AA+1,12) AT=MOD(AT+1,8) DET=DET+1 ID=ID+3 CA=CA+1 CT1=CT1+1 CT2=CT2+1 NA=CA/12*DSA+NADC NT1=CT1/8*DST1+NTDC1 NT2=CT2/8*DST2+NTDC2 IF(PAT.NONE.[B])LEND ;TEST PATTERN REG BIT OUT 8000H+ID ;OUTPUT PARAMETER ID ROUT NA,AA,0 ;N,A = , ROUT NT1,AT,0 ;N,A = , ROUT NT2,AT,0 ;N,A = , LEND ENDLOOP ;END OF LOOP * * * * NESTED LOOPS ARE NOT SUPPORTED * * * * Page 38 PROGRAMMING EXAMPLES (continued) COM$ EXAMPLE EVENT-HANDLER PROGRAM PGM$ S=12 ;STOP BIT = 12 W=11 ;WAIT BIT = 11 E=10 ;EVENT BIT = 10 M=1 ;MASTER BIT IN GATED LATCH NAD1=5 ;ADC1 IN SLOT 5 NLAT=2 ;GATED LATCH IN SLOT 2 SETB ;SET BUSY TO INIT CAMAC INIT IF(EX.ANY.[S,W])INIT ;WAIT FOR EXT HANGUPS TO END CLR NAF NAD1,12,11 ;CLEAR ADC NAF NLAT,0,9 ;CLEAR LATCH WAIT IF(EX.ANY.[S,W])WAIT ;WAIT FOR EXT STOPS AND WAIT STATES CLRB ; * GO * IDLE IF(EX.NONE.[S,W,E])IDLE ;LOOP UNTIL SOMETHING HAPPENS IF(EX.ANY.[S,W])STOP ;STOP OR WAIT IF(EX.NONE.[E])IDLE ;? - WELL , GO BACK AND TRY AGAIN SETB ;PREPARE TO READ OUT DLAY 1000 ;WAIT FOR CONVERSIONS SPAT NLAT,0,0 ;GET GATED LATCH SIGNAL IF(PAT.NONE.[M])CLR ;IF MASTER COUNTER DID NOT FIRE,IGNORE OUT 8001H ;EVENT HEADER OUT CA ;LATCH TO FIFO A=-1 ;SET UP ADC READ LOOP LOOP 8 A=A+1 ;INC ADDRESS ROUT NAD1,A,0 ;ADC TO FIFO ENDLOOP OUT 0FFFFH ;END OF EVENT BRU CLR ;GO AND RESET ADCS ETC STOP SETB ;STOP - SET BUSY BRU WAIT ;AND GO INTO WAIT STATE END PROGRAMMING EXAMPLES Loops are initiated by the LOOP directive and terminated by the ENDLOOP (equivalent to CONTINUE in Fortran). An example is shown below: SPAT 1,1,0 ;RED & STORE PATTERN REGISTER B=0 ;INIT PATTERN REG BIT COUNTER AA=-1 ;INIT ADC SUB-ADDR CNTR AT=-1 ;INIT TDC SUB-ADDR CNTR DET=0 ;INIT DETECTOR COUNTER ID=-2 ;INIT PARM ID # NADC=10 ;SLOT FOR ADC (ADC IN 10 & 11) NTDC1=12 ;SLOT FOR TDC1 (TDC1 IN 12 & 13) NTDC2=7 ;SLOT FOR TDC2 (TDC2 IN 7 & 9) DSA=1 ;SLOT INC FOR ADC DST1=1 ;SLOT INC FOR TDC1 Page 39 DST2=2 ;SLOT INC FOR TDC2 CA=-1 ;CNTR FOR ADC SLOT SWITCHING CT1=-1 ;CNTR FOR TDC1 SLOT SWITCHING CT2=-1 ;CNTR FOR TDC2 SLOT SWITCHING LU1 LOOP 16 B=B+1 AA=MOD(AA+1,12) AT=MOD(AT+1,8) DET=DET+1 ID=ID+3 CA=CA+1 CT1=CT1+1 CT2=CT2+1 NA=CA/12*DSA+NADC NT1=CT1/8*DST1+NTDC1 NT2=CT2/8*DST2+NTDC2 IF(PAT.NONE.[B])LEND ;TEST PATTERN REG BIT OUT 8000H+ID ;OUTPUT PARAMETER ID ROUT NA,AA,0 ;N,A = , ROUT NT1,AT,0 ;N,A = , ROUT NT2,AT,0 ;N,A = , LEND ENDLOOP ;END OF LOOP * * * * NESTED LOOPS ARE NOT SUPPORTED * * * * Page 40 PROGRAMMING EXAMPLES (continued) COM$ EXAMPLE EVENT-HANDLER PROGRAM PGM$ S=12 ;STOP BIT = 12 W=11 ;WAIT BIT = 11 E=10 ;EVENT BIT = 10 M=1 ;MASTER BIT IN GATED LATCH NAD1=5 ;ADC1 IN SLOT 5 NLAT=2 ;GATED LATCH IN SLOT 2 SETB ;SET BUSY TO INIT CAMAC INIT IF(EX.ANY.[S,W])INIT ;WAIT FOR EXT HANGUPS TO END CLR NAF NAD1,12,11 ;CLEAR ADC NAF NLAT,0,9 ;CLEAR LATCH WAIT IF(EX.ANY.[S,W])WAIT ;WAIT FOR EXT STOPS AND WAIT STATES CLRB ; * GO * IDLE IF(EX.NONE.[S,W,E])IDLE ;LOOP UNTIL SOMETHING HAPPENS IF(EX.ANY.[S,W])STOP ;STOP OR WAIT IF(EX.NONE.[E])IDLE ;? - WELL , GO BACK AND TRY AGAIN SETB ;PREPARE TO READ OUT DLAY 1000 ;WAIT FOR CONVERSIONS SPAT NLAT,0,0 ;GET GATED LATCH SIGNAL IF(PAT.NONE.[M])CLR ;IF MASTER COUNTER DID NOT FIRE,IGNORE OUT 8001H ;EVENT HEADER OUT CA ;LATCH TO FIFO A=-1 ;SET UP ADC READ LOOP LOOP 8 A=A+1 ;INC ADDRESS ROUT NAD1,A,0 ;ADC TO FIFO ENDLOOP OUT 0FFFFH ;END OF EVENT BRU CLR ;GO AND RESET ADCS ETC STOP SETB ;STOP - SET BUSY BRU WAIT ;AND GO INTO WAIT STATE END